FIG. 5 is a block diagram illustrating a structure of a prior art buffer memory control device. In FIG. 5, buffer memories 11a to 11d and 12a to 12d are included in a data output device 10. Buffer memories 21a to 21d and 22a to 22d are included in a data output device 20. A storage device 100 is connected to the data output device 10. A storage device 200 is connected to the data output device 20. An interface circuit 110 is used for controlling the storage device 100. An interface circuit 210 is used for controlling the storage device 200. Data receiving devices (client terminals) 4a to 4d are used for issuing transfer request of data. A switching device 50 (hub) is used for connecting outputs from the data output devices 10 and 20 to the data receiving devices 4a to 4d.
Data of files A, B, C, and D (not shown) is respectively divided into block data A1, A2, . . . , B1, B2, . . . , C1, C2 . . . D1, D2, . . . of 256 KB, which are stored in the storage devices 100 and 200. As an example of this, a structure of the file A is shown in FIG. 6. In FIG. 6, reference numerals 1, 2 and 3 designate a file A which is divided into a small block of 1 KB, a block A1 of 256 KB consisting of small blocks 1 to 256 of the file A, and a block A2 of 256 KB consisting of small blocks 257 to 512 subsequent to the block A1, respectively. In this way, the file A is divided into plural blocks of 256 KB. As shown in FIG. 5, blocks A1, A3, . . . , of odd numbers, and blocks A2, A4, . . . , of even numbers are stored in storage devices 100 and 200, respectively. Similarly, the file B is divided into data B1 to B6 and stored in the storage devices 100 and 200, the file C is divided into data C1 to C6 and stored in the storage devices 100 and 200, and the file D is divided into data D1 to D6 and stored in the storage devices 100 and 200, although these are not shown in Figures.
A method of simultaneously transmitting data of the file A to the data receiving device 4a, data of the file B to the data receiving device 4b, data of the file C to the data receiving device 4c, and data of the file D to the data receiving device 4d is disclosed in Japanese Patent Application No. 5-35407 and will be described with reference to FIG. 7. FIG. 7 is a diagram illustrating a relation between data readout from a storage device and data output to the data receiving device every cycle in the prior art buffer memory control device.
In a first cycle, the data output device 10 reads the block data A1 from the storage device 100 and temporarily stores the block data A1 in the buffer memory 11a. Then, the data output device 10 reads the block data B1 from the storage device 100 and temporarily stores the block data B1 in the buffer memory 11b. The data output device 20 reads the block data C2 from the storage device 200 and temporarily stores the block data C2 in the buffer memory 21c. Then, the data output device 20 reads the block data D2 from the storage device 200 and temporarily stores the block data D2 in the buffer memory 21d.
In a second cycle, the data output device 10 reads the block data C3 from the storage device 100 and temporarily stores the block C3 in the buffer memory 11C. Then, the data output device 10 reads the block data D3 from the storage device 100 and temporarily stores the block data D3 in the buffer memory 11d. The data output device 20 reads the block data A2 from the storage device 200 and temporarily stores the block data A2 in the buffer memory 21a. Then, the data output device 20 reads the block data B2 from the data storage device 200 and temporarily stores the block data B2 in the buffer memory 21b. In addition, the data output device 10 outputs the block data A1 temporarily stored in the buffer memory 11a to the data receiving device 4a and simultaneously outputs the block data B1 temporarily stored in the buffer memory 11b to the data receiving device 4b via the switching device 50. The data output device 20 outputs the block data C2 temporarily stored in the buffer memory 21c to the data receiving device 4c and simultaneously outputs the block data D2 temporarily stored in the buffer memory 21d to the data receiving device 4d via the switching device 50.
In a third cycle, the data output device 10 reads the block data A3 from the storage device 100 and temporarily stores the block data A3 in the buffer memory 12a. Then, the data output device 10 reads the block data B3 from the storage device 100 and temporarily stores the block data B3 in the buffer memory 12b. The data output device 20 reads the block data C4 from the storage device 200 and temporarily stores the block data C4 in the buffer memory 22c. Then, the data output device 20 reads the block data D4 from the storage device 200 and temporarily stores the block data D4 in the buffer memory 22d. In addition, the data output device 10 outputs the block data C3 temporarily stored in the buffer memory 11c to the data receiving device 4c and simultaneously outputs the block data D3 temporarily stored in the buffer memory lid to the data receiving device 4d via the switching device 50. The data output device 20 outputs the block data A2 temporarily stored in the buffer memory 21a to the data receiving device 4a and simultaneously outputs the block data 12 temporarily stored in the buffer memory 21b to the data receiving device 4b via the switching device 50.
It should be noted that starting of data transfer from the data output device 10 in the third cycle is delayed if data transfer from the data output device 10 to the data receiving device 4a or to the data receiving device 4b is not completed in the second cycle. In some files, a data transfer rate requested by the data receiving device is low, and it is not possible to specify when switching from the data output device 10 to the data output device 20 is performed. Switching between these output devices is identical to those of the files B, C and D. When data is smoothly transferred, a video-file-1 and a video-file-2 are switched every given time and sequentially read from the data output devices 10 and 20 at maximum transfer efficiency 1.5 Mbps as shown in FIG. 8. When readout of the video file 1 is not completed by the time readout of the subsequent video file 2 is started, readout period of the video file 1 is overlapped with readout period of the video file 2 as shown FIG. 9, data with a maximum efficiency that is higher than 1.5 Mbps cannot be read properly and such data is deserted or a screen is temporarily stopped until readout of the video file 1 is completed and display is resumed after readout of the video file 1 is completed.
In a fourth cycle, the data output device 10 reads the block data C5 from the storage device 100 and temporarily stores the block data C5 in the buffer memory 12c. Then, the data output device 10 reads the block D5 from the storage device 100 and temporarily stores the block data D5 in the buffer memory 12d. The data output device 20 reads the block data A4 from the storage device 200 and temporarily stores the block data A4 in the buffer memory 22a. Then, the data output device 20 reads the block data B4 from the data storage device 200 and temporarily stores the block data B4 in the buffer memory 22b. In addition, the data output device 10 outputs the block data A3 temporarily stored in the buffer memory 12a to the data receiving device 4a and simultaneously outputs the block data B3 temporarily stored in the buffer memory 12b to the data receiving device 4b via the switching device 50. The data output device 20 outputs the block data C4 temporarily stored in the buffer memory 22c to the data receiving device 4c and simultaneously outputs the block data D4 temporarily stored in the buffer memory 22d to the data receiving device 4d via the switching device 50.
In subsequent cycles, as in the first to fourth cycles, the data output devices 10 and 20 each reads a block to be read and temporarily stores the block in an allocated buffer memory, and then in the following cycle, they output the blocks to the data receiving devices 4a to 4d, respectively. This processing is repeated till the last file. In this way, alternate switching is performed between buffer memories for readout from the storage devices 100 and 200 and buffer memories for data output to the data receiving devices, thereby it is possible to sequentially output data of files with various transfer rates. In order to output data to 4 data receiving devices, the data output devices 10 and 20 each requires buffer memories of 256 KB.times.8, resulting in a total memory capacity of 4 KB in the entire system.
In the prior art memory control device constructed above, buffer memories for readout and buffer memories for data output to the data receiving device are alternately switched, thereby it is possible to continuously output data of files with various transfer rates. However, there has been a problem that use of this construction causes a large total capacity of buffer memories and high cost in the entire system. If a size of a buffer memory is reduced to lower cost, amount of data that can be read from the storage devices 100 and 200 in one readout is reduced, resulting in a shorter time for use in data readout and higher frequency of access to data for reading data of the same capacity. In is the storage devices 100 and 200, there is a seek time as a moving time of head for reading data from a disk or a loss time such as a waiting time before an area of storage rotates to a vicinity of a head as in the general-use hard disk drive (HDD). For this reason, if a size of a buffer memory is reduced and frequency of access is increased, most of the time in a cycle is occupied with the seek time or loss time. Consequently, amount of data that can be read from the data storage devices 100 and 200 in a given time is reduced and accordingly amount of data that is output from the data output devices 10 and 20 every cycle is reduced, resulting in fewer data receiving devices that can output data.